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5
PRELIMINARY
CY7C1355V25 CY7C1357V25
256Kx36/512Kx18 Flow-Thru SRAM with NoBLTM Architecture
Features
* Pin compatible and functionally equivalent to ZBTTM devices * Supports 133-MHz bus operations with zero wait states -- Data is transferred on every clock * Internally self-timed output buffer control to eliminate the need to use asynchronous OE * Registered inputs for Flow-Through operation * Byte Write capability * Common I/O architecture * Single 2.5V power supply * Fast clock-to-output times -- 6.5 ns (for 133-MHz device) -- 7.5 ns (for 117-MHz device) -- 8.5 ns (for 100-MHz device) -- 10.0 ns (for 80-MHz device) * Clock Enable (CEN) pin to suspend operation * Synchronous self-timed writes * Available in 100 TQFP & 119 BGA Packages * Burst Capability--linear or interleaved burst order respectively. They are designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355V25/CY7C1357V25 is equipped with the advanced No Bus LatencyTM (NoBLTM) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1355V25/CY7C1357V25 is pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the Byte Write Selects (BWSa,b,c,d for CY7C1355V25 and BWSa,b for CY7C1357V25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.
Functional Description
The CY7C1355V25 and CY7C1357V25 are 2.5V, 256K by 36 and 512K by 18 Synchronous-Flow-Through Burst SRAMs,
Logic Block Diagram
CLK CE ADV/LD Ax CEN CE 1 CE2 CE3 WE BWSx Mode CONTROL and WRITE LOGIC 256KX36/ 512KX18 MEMORY ARRAY D Data-In REG. Q
DQx DPx
CY7C1355 AX DQX DPX BWS X X = 17:0 X= a, b, c, d X = a, b, c, d X = a, b, c, d
CY7C1357 X = 18:0 X = a, b X = a, b X = a, b
OE
Selection Guide
7C1355V25-133 7C1357V25-133 Maximum Access Time (ns) Maximum Operating Current (mA)
Shaded areas contain advance information. No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology.
7C1355V25-117 7C1357V25-117 7.5 280 10
7C1355V25-100 7C1357V25-100 8.5 250 10
7C1355V25-80 7C1357V25-80 10.0 200 10
6.5 Com'l 300 10
Maximum CMOS Standby Current (mA) Com'l
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 December 2, 1999
PRELIMINARY
Pin Configurations
100-Pin TQFP Packages
CY7C1355V25 CY7C1357V25
A A CE1 CE2 BWSd BWSc BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD NC A
A A CE1 CE2 NC NC BWSb BWSa CE3 VDD VSS CLK WE CEN OE ADV/LD NC A
DPb DQb DQb VDDQ VSS NC NC NC V DDQ V SS NC NC DQb DQb VSS VDDQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DPc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ
DQc DQc V SS VDD VDD VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQb DQb DQb DQb VSS VDDQ DQb DQb DQb DQb VSS Vss V DD VDD V DD VDD VSS NC DQb DQa DQa DQb VDDQ V DDQ VSS VSS DQa DQb DQa DQb DQa DPb DQa NC VSS V SS VDDQ VDDQ DQa NC DQa NC NC DPa
A A
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DPa DQa DQa VSS VDDQ DQa DQa VSS VDD VDD NC DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC
CY7C1355V25 (256K x 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
CY7C1357V25 (512K x 18)
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 DNU DNU V SS VDD
DNU DNU A A A A A A A
MODE A A A A A1 A0 DNU DNU VSS VDD
DNU DNU A A A A A A
2
A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PRELIMINARY
Pin Configurations (continued)
119-Ball Bump BGA CY7C1355 (256K x 36) - 7 x 17 BGA
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQ d VDDQ DQ d DQd NC NC VDDQ
CY7C1355V25 CY7C1357V25
2
A CE2 A DPc DQc DQ c DQc DQ c VDD DQd DQ d DQd DQ d DPd A 64M TMS
3
A A A VSS VSS VSS BWSc VSS VSS(1) VSS BWSd VSS VSS VSS MODE A TDI
4
16M ADV/LD VDD NC CE 1 OE A WE VDD CLK NC CEN A1 A0 VDD A TCK
5
A A A VSS VSS VSS BWSb VSS VSS(1) VSS BWS a VSS VSS VSS VSS A TDO
6
A CE3 A DPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DPa A 32M DNU
7
VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC NC VDDQ
CY7C1357 (512K x 18) - 7 x 17 BGA
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQ b NC VDDQ NC DQ b VDDQ NC DQ b VDDQ DQ b NC NC 64M VDDQ
2
A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DPb A A TMS
3
A A A VSS VSS VSS BWS b VSS VSS(1) VSS VSS VSS VSS VSS MODE A TDI
4
16M ADV/LD VDD NC CE 1 OE A WE VDD CLK NC CEN A1 A0 VDD 32M TCK
5
A A A VSS VSS VSS VSS VSS VSS(1) VSS BWSa VSS VSS VSS VSS A TDO
6
A CE3 A DPa NC DQa NC DQa VDD NC DQa NC DQa NC A A DNU
7
VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC NC VDDQ
3
PRELIMINARY
Pin Definitions (100-Pin TQFP)
x18 Pin Location 37, 36, 32-35, 44-50,80-83, 99, 100 93, 94 x36 Pin Location 37, 36, 32-35, 44-50, 81-83, 99, 100 93, 94, 95, 96 Name A0 A1 A BWS a BWS b BWS c BWS d WE I/O Type InputSynchronous InputSynchronous
CY7C1355V25 CY7C1357V25
Description Address Inputs used to select one of the 266,144 address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWS b controls DQb and DPb, BWS c controls DQc and DPc, BWSd controls DQ d and DPd. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.
88
88
InputSynchronous InputSynchronous
85
85
ADV/LD
89
89
CLK
Input-Clock
98
98
CE1
InputSynchronous InputSynchronous InputSynchronous
97
97
CE2
92
92
CE3
86
86
OE
InputOutput Enable, active LOW. Combined with the synchroAsynchronous nous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence , during the first clock when emerging from a deselected state and when the device has been deselected. InputSynchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ a-DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.
87
87
CEN
(a)58, 59, 62, 63, 68, 69, 72-74, (b)8, 9, 12, 13, 18, 19, 22-24
(a)52, 53, 56-59, 62, 63, (b)68, 69, 72-75, 78, 79, (c)2, 3, 6-9, 12, 13, (d)18, 19, 22-25, 28, 29
DQa DQb DQc DQd
I/OSynchronous
4
PRELIMINARY
Pin Definitions (100-Pin TQFP) (continued)
x18 Pin Location 74, 24 x36 Pin Location 51, 80, 1, 30 Name DPa DPb DPc DPd MODE I/O Type I/OSynchronous
CY7C1355V25 CY7C1357V25
Description Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DPa is controlled by BWSa, DPb is controlled by BWSb, DPc is controlled by BWSc, and DPd is controlled by BWSd. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. Power supply inputs to the core of the device. Power supply for the I/O circuitry. Ground for the device. Should be connected to ground of the system. No connects. Reserved for address expansion to 512K depths. Do Not Use pins. These pins should be left floating.
31
31
Input Strap pin
15 , 41, 65, 66, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 14, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90
15 , 41, 65, 66, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 14,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
VDD VDDQ VSS
Power Supply I/O Power Supply Ground
NC 38, 39, 42, 43 38, 39, 42, 43 DNU
-
5
PRELIMINARY
Pin Definitions (119 BGA)
x18 Pin Location P4, N4, A2, A3, A5, A6, B3, B5, C2, C3, C5, C6, G4, R2, R6, T2, T3, T5, T6 L5, G3 x36 Pin Location P4, N4, A2, A3, A5, A6, B3, B5, C2, C3, C5 C6, R2, R6, G4, T3, T4, T5 L5, G5, G3, L3 Name A0 A1 A BWSa BWSb BWSc BWSd WE I/O Type InputSynchronous
CY7C1355V25 CY7C1357V25
Description Address Inputs used to select one of the 266,144 address locations. Sampled at the rising edge of the CLK.
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWS a controls DQa and DPa, BWSb controls DQb and DPb, BWSc controls DQ c and DPc, BWSd controls DQd and DPd. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence , during the first clock when emerging from a deselected state and when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[x:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa-DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.
H4
H4
InputSynchronous
B4
B4
ADV/LD InputSynchronous
K4
K4
CLK
Input-Clock
E4
E4
CE1
InputSynchronous InputSynchronous InputSynchronous InputAsynchronous
B2
B2
CE2
B6
B6
CE3
F4
F4
OE
M4
M4
CEN
InputSynchronous
(a)P7, N6, L6, K7, H6, G7, F6, E7 (b)N1, M2, L1, K2, H1, G2, E2, D1
(a)P7, N7, N6, M6, L7, L6, K7, K6 (b)D7, E7, E6, F6, G7, G6, H7, H6 (c)D1, E1, E2, F2, G1, G2, H1, H2 (d)P1, N1, N2, M2, L1, L2, K1, K2
DQa DQb DQc DQd
I/OSynchronous
6
PRELIMINARY
Pin Definitions (119 BGA) (continued)
x18 Pin Location D6, P2 x36 Pin Location P6, D6, D2, P2 Name DPa DPb DPc DPd MODE I/O Type I/OSynchronous
CY7C1355V25 CY7C1357V25
Description Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQa-DQ d. During write sequences, DPa is controlled by BWS a, DPb is controlled by BWS b, DPc is controlled by BWSc, and DPd is controlled by BWSd. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. Power supply inputs to the core of the device. Power supply for the I/O circuitry. Ground for the device. Should be connected to ground of the system.
R3
R3
Input Strap Pin
C4, J2, J4, J6, R4 A1, A7, F1, F7, J1, J7, M1, M7, U1, U7 D3, D5, E3, E5, F3, F5, H3, H5, K3, K5, M3, M5, N3, N5, P3, P5, R5 T7 J3, J5 U5
C4, J2, J4, J6, R4
VDD
Power Supply I/O Power Supply Ground
A1, A7, F1, F7, J1 VDDQ J7, M1, M7, U1, U7 D3, D5, E3, E5, F3, F5, H3, H5, K3, K5, M3, M5, N3, N5, P3, P5, R5 T7 J3, J5 U5 VSS
ZZ VSS(1) TDO
These pins have to be tied to a voltage level < Vil. They need not be tied to VSS. JTAG Serial Output, Synchronous JTAG Serial Input, Synchronous Test Mode Select, Synchronous JTAG Serial Output, Synchronous Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. No connects. Reserved for address expansion.
U3
U3
TDI
U2
U2
TMS
U4
U4
TCK
A4, T6, T2
A4, T4, T1
16M, 32M 64M NC
B1, B7, C1, C7, D2, D4, D7, E1, E6, F2, G1, G5, G6, H2, H7, J3, J5, K1, K6, L2,L3, L4, M6, N2, N7, P1, P6, R1, R7 U6
B7, C7, D4, J3, J5, L4, R1, R7, T1
-
No connects.
U6
DNU
-
Do not use pin.
7
PRELIMINARY
Introduction
Functional Overview The CY7C1355V25/CY7C1357V25 is a Synchronous FlowThrough Burst NoBL SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns (133-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a Read or Write operation, depending on the status of the Write Enable (WE). Byte Write Selects can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE 2, CE 3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. The data is available within 6.5 ns (133MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. On the subsequent clock, another operation (Read/Write/Deselect) can be initiated. When the SRAM is deselected at clock rise by one of the chip enable signals, its output will be three-stated immediately. Burst Read Accesses The CY7C1355V25/CY7C1357V25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved
CY7C1355V25 CY7C1357V25
burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ and DP. On the next clock rise the data presented to DQ and DP (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by Byte Write Select signals. The CY7C1355V25/CY7C1357V25 provide byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A Synchronous selftimed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1355V25/CY7C1357V25 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ and DP inputs. Doing so will three-state the output drivers. As a safety precaution, DQ and DP are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1355V25/CY7C1357V25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE 3) and WE inputs are ignored and the burst counter is incremented. The correct BWS a,b,c,d/BWS a,b inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.
8
PRELIMINARY
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Operation Deselected Suspend Begin Read Begin Write Burst READ Operation Address used External External External Internal CE 1 X 0 0 X CEN 0 1 0 0 0 ADV/ LD 0 X 0 0 1 WE X X 1 0 X BWSx X X X Valid X CLK L-H L-H L-H L-H L-H
CY7C1355V25 CY7C1357V25
Comments I/Os three-state following next recognized clock. Clock ignored, all operations suspended. Address latched. Address latched, data presented two valid clocks later. Burst Read operation. Previous access was a Read operation. Addresses incremented internally in conjunction with the state of MODE. Burst Write operation. Previous access was a Write operation. Addresses incremented internally in conjunction with the state of MODE. Bytes written are determined by BWSa,b,c,d/BWS a,b.
Burst WRITE Operation
Internal
X
0
1
X
Valid
L-H
Interleaved Burst Sequence
First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 00 11 10 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 10 01 00
Linear Burst Sequence
First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 10 11 00 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 00 01 10
Notes: 1. X = "don't care," 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables. CE = 0 stands for ALL Chip Enables are active. 2. Write is defined by WE and BWSx. BWSx = Valid signifies that the desired byte write selects are asserted. See Write Cycle Description table for details. 3. The DQ and DP pins are controlled by the current cycle and the OE signal. 4. CEN = 1 inserts wait states. 5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 6. OE assumed LOW.
9
PRELIMINARY
Write Cycle Description[1]
Function (CY7C1355V25) Read Write - No Bytes Written Write Byte 0 - (DQa and DPa) Write Byte 1 - (DQb and DPb) Write Bytes 1, 0 Write Byte 2 - (DQc and DPc) Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes 2, 1, 0 Write Byte 3 - (DQb and DPd) Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes 3, 1, 0 Write Bytes 3, 2 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 Write All Bytes Function (CY7C1357V25) Read Write - No Bytes Written Write Byte 0 - (DQ a and DPa) Write Byte 1 - (DQ b and DPb) Write Both Bytes WE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BWSd X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 WE 1 0 0 0 0 BWSc X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 BWSb x 1 1 0 0
CY7C1355V25 CY7C1357V25
BWSb X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
BWSa X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 BWS a x 1 0 1 0
10
PRELIMINARY
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1355V25/57V25 incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port (TAP) - Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (See TAP Controller State diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the
CY7C1355V25 CY7C1357V25
instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a xx-bit-long register, and the x18 configuration has a yy-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the SRAM and cannot preload the Input or Output buffers. The
11
PRELIMINARY
SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE / PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the ShiftIR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE / PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE / PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE / PRELOAD SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant.
CY7C1355V25 CY7C1357V25
When the SAMPLE / PRELOAD instructions are loaded into the instruction register and the TAP controller is in the CaptureDR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE / PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the UpdateDR state while performing a SAMPLE / PRELOAD instruction will have the same effect as the Pause-DR command. Bypass When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
12
PRELIMINARY
TAP Controller State Diagram
CY7C1355V25 CY7C1357V25
1
TEST-LOGIC RESET 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 CAPTURE-DR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 0 1 0
0
TEST-LOGIC/ IDLE
1
SELECT DR-SCAN 0 1
1
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
13
PRELIMINARY
TAP Controller Block Diagram
CY7C1355V25 CY7C1357V25
0 Bypass Register Selection Circuitry TDI Selection Circuitry TDO
2 Instruction Register
1
0
31 30
29
.
.
2
1
0
Identification Register
x
.
.
.
.
2
1
0
Boundary Scan Register
TCK TAP Controller TMS
TAP Electrical Characteristics Over the Operating Range[7, 8]
Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND V I VDDQ IOH = -2.0 mA IOH = -100 A IOL = 2.0 mA IOL = 100 A 1.7 -0.3 -5 Test Conditions Min. 1.7 2.1 0.7 0.2 VDD+0.3 0.7 5 Max. Unit V V V V V V A
Notes: 7. All Voltage referenced to Ground. 8. Overshoot: VIH(AC)14
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter tTCYC tTF tTH tTL Set-up Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 10 10 10 TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 10 10 10 TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 40 40 Description Min. 100
CY7C1355V25 CY7C1357V25
Max
Unit ns
10
MHz ns ns
ns ns ns
ns ns ns
20
ns ns
Notes: 9. t CS and t CH refer to the set-up and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC test conditions. tR/tF= 1 ns.
15
PRELIMINARY
TAP Timing and Test Conditions
CY7C1355V25 CY7C1357V25
1.25V 50 TDO Z0 =50 CL =20 pF 0V ALL INPUT PULSES 2.5V 1.25V
GND
(a)
(b)
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data-In TDI
Test Data-Out TDO
tTDOX
tTDOV
16
PRELIMINARY
Identification Register Definitions
Instruction Field Revision Number (31:28) Device Depth (27:23) Device Width (22:18) Cypress Device ID (17:12) Cypress JEDEC ID (11:1) ID Register Presence (0) TBD TBD TBD TBD TBD TBD Value Description Reserved for version number. Defines depth of SRAM. Defines with of the SRAM. Reserved for future use.
CY7C1355V25 CY7C1357V25
Allows unique identification of SRAM vendor. Indicate the presence of an ID register.
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan 3 1 32 TBD Bit Size
Identification Codes
Instruction EXTEST 000 Code Description Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD
001 010 011 100
RESERVED RESERVED BYPASS
101 110 111
17
PRELIMINARY
Boundary Scan Order
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
CY7C1355V25 CY7C1357V25
Boundary Scan Order
Bit # 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bit # Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
18
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied .................................................. -55C to +125C Supply Voltage on VDD Relative to GND .........-0.5V to +3.6V DC Voltage Applied to Outputs in High Z State[12]....................................-0.5V to VDDQ + 0.5V DC Input Voltage[12] ................................-0.5V to VDDQ + 0.5V
CY7C1355V25 CY7C1357V25
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Range Com'l Ambient Temperature[11] 0C to +70C VDD/VDDQ 2.5V 5%
Electrical Characteristics Over the Operating Range
Parameter VDD VDDQ VOH VOL VIH VIL IX IOZ IDD Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[12] Input Load Current Input Current of MODE Output Leakage Current VDD Operating Supply GND V I VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz 8.5-ns cycle, 117 MHz 10-ns cycle, 100 MHz 12-ns cycle, 80 MHz ISB1 Automatic CE Power-Down Current--TTL Inputs Max. V DD, Device Deselected, VIN VIH or VIN V IL f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz 8.5-ns cycle, 117 MHz 10-ns cycle, 100 MHz 12-ns cycle, 80 MHz ISB2 Automatic CE Power-Down Current--CMOS Inputs Automatic CE Power-Down Current--CMOS Inputs Automatic CE Power-Down Current--TTL Inputs Max. V DD, Device Deselected, VIN 0.3V or VIN > VDDQ - 0.3V, f=0 Max. VDD, Device Deselected, or VIN 0.3V or VIN > VDDQ - 0.3V, f = fMAX = 1/tCYC All speed grades GND V I VDDQ VDD = Min., IOH = -1.0 mA[13] VDD = Min., IOL = 1.0 mA
[13]
Test Conditions
Min. 2.375 2.375 2.0
Max. 2.625 2.625 0.2
Unit V V V V V V A A A mA mA mA mA mA mA mA mA mA
1.7 -0.3 -5 -30 -5
VDD + 0.3V 0.7 5 30 5 300 280 250 200 90 80 70 65 10
ISB3
7.5-ns cycle, 133 MHz 8.5-ns cycle, 117 MHz 10-ns cycle, 100 MHz 12-ns cycle, 80 MHz
45 40 35 30 25
mA mA mA mA mA
ISB4
Max. V DD, Device Deselected, VIN VIH or VIN V IL, f = 0
All speed grades
Notes: 11. TA is the case temperature. 12. Minimum voltage equals -2.0V for pulse durations of less than 20 ns. 13. The load used for VOH and VOL testing is shown in figure (b) of the AC Test Loads.
19
PRELIMINARY
Capacitance[15]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = VDDQ = 2.5V Max. 4 4 4
CY7C1355V25 CY7C1357V25
Unit pF pF pF
AC Test Loads and Waveforms
OUTPUT Z0 =50 RL =50 VL = 1.25V 2.5V OUTPUT 5 pF R=1538 INCLUDING JIG AND SCOPE R=1667 ALL INPUT PULSES 2.5V 10% GND 2.0 ns 90%
[14]
90% 10% 2.0 ns
(a)
(b)
(c)
Thermal Resistance
Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case)
Notes: 14. Input waveform should have a slew rate of > 1 V/ns. 15. Tested initially and after any design or process change that may affect these parameters.
Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board.
Symbol JA JC
TQFP Typ. TBD TBD
Units C/W C/W
Notes 15 15
20
PRELIMINARY
Switching Characteristics Over the Operating Range[16]
-133 Parameter Clock tCYC FMAX tCH tCL Clock Cycle Time Maximum Operating Frequency Clock HIGH Clock LOW 1.9 1.9 7.5 133 1.9 1.9 8.5 117 1.9 1.9 10.0 100 Description Min. Max. -117 Min. Max. 100 Min. Max.
CY7C1355V25 CY7C1357V25
80 Min. Max. Unit
15.0 80 4.0 4.0
ns MHz ns ns
Output Times tCDV tEOV tDOH tCHZ tCLZ tEOHZ tEOLZ Data Output Valid After CLK Rise OE LOW to Output Valid[15, 17] Data Output Hold After CLK Rise Clock to High-Z Clock to Low-Z
[18, 19, 17]
6.5 4.0 1.5 1.5 3 4.0 0 0 4.0 1.5 1.5 3
7.5 4.2 1.5 4.2 1.5 3 4.2 0
8.5 5.0 1.5 5.0 1.5 3 5.0 0
10.0 5.0
ns ns ns
5.0
ns ns
[18, 19, 17]
OE HIGH to Output High-Z[18, 19, 17] OE LOW to Output Low-Z
[18, 19, 17]
5.0
ns ns
Set-up Times tAS tDS tCENS tWES tALS tCES Hold Times tAH tDH tCENH tWEH tALH tCEH Address Hold After CLK Rise Data Input Hold After CLK Rise CEN Hold After CLK Rise WE, BWx Hold After CLK Rise ADV/LD Hold after CLK Rise Chip Select Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Set-Up Before CLK Rise Data Input Set-Up Before CLK Rise CEN Set-Up Before CLK Rise WE, BWSx Set-Up Before CLK Rise ADV/LD Set-Up Before CLK Rise Chip Select Set-Up 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns ns ns ns ns ns
Shaded areas contain advance information. Notes: 16. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and output loading of the specified I OL/IOH and load capacitance. Shown in (a), (b) and (c) of AC test loads.. 17. This parameter is sampled and not 100% tested. 18. t CHZ, t CLZ, tOEV, t EOLZ, and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured 200 mV from steadystate voltage. 19. At any given voltage and temperature, t EOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.
21
PRELIMINARY
Switching Waveforms
Read/Write/Deselect Sequence
CY7C1355V25 CY7C1357V25
DESELECT
Write
Read
Suspend
DESELECT
CLK
tCENS tCENH tCH tCL tCYC tCENS tCENH
CEN
tAS
ADDRESS
RA1
WA2
RA3
RA4
WA5
RA6
RA7
tAH
WE
tWES tCES tWEH
tCEH
CE
tCHZ tCHZ D2 In Q3 Out Q4 Out D5 In Q6 Out tDOH Q7 Out
tCLZ
tDOH Q1 Out
DataIn/Out
Device tCDV originally deselected
WE is the combination of WE & BWSx(x = a, b, c, d) to define a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip selects need to be active in order to select the device. Any chip select can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X.
= DON'T CARE
= UNDEFINED
22
DESELECT
Read
Read
Write
Read
Read
PRELIMINARY
Switching Waveforms (continued)
Burst Sequences
Begin Read Burst Read Burst Read Burst Read Begin Read Begin Write Burst Write Burst Write Burst Write
CY7C1355V25 CY7C1357V25
CLK
tALS tALH tCH tCL tCYC
ADV/LD
tAS tAH
ADDRESS
RA1
WA2
RA3
WE
tWES tWEH tWS tWH
BWSx
tCES tCEH
CE
tDOH Q1 1a Out tCDV t DeviceCDV originally deselected Q1+1 Out Q1+2 Out tCHZ Q1+3 Out tDS tDH D2 In D2+1 In D2+2 In tCLZ D2+3 In Q3 Out Q3+1 Out
tCLZ
DataIn/Out
The combination of WE & BWS x(x = a, b, c, d) define a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWSx input signals. Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW. = DON'T CARE = UNDEFINED
23
Burst Read
Burst Read
PRELIMINARY
Switching Waveforms (continued)
OE Timing
CY7C1355V25 CY7C1357V25
OE
tEOHZ tEOV
I/O's
Three-state
tEOLZ
Ordering Information
Speed (MHz) 133 Ordering Code CY7C1355V25-133AC/ CY7C1357V25-133AC CY7C1355V25-133BGC/ CY7C1357V25-133BGC 117 CY7C1355V25-117AC/ CY7C1357V25-117AC CY7C1355V25-117BGC/ CY7C1357V25-117BGC 100 CY7C1355V25-100AC/ CY7C1357V25-100AC CY7C1355V25-100BGC/ CY7C1357V25-100BGC 80 CY7C1355V25-80AC/ CY7C1357V25-80AC CY7C1355V25-80BGC/ CY7C1357V25-80BGC
Shaded areas contain advance information.
Package Name A101 BG119 A101 BG119 A101 BG119 A101 BG119
Package Type 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead FBGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead FBGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead FBGA (14 x 22 x 2.4 mm) 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack 119-Lead FBGA (14 x 22 x 2.4 mm)
Operating Range Commercial
Document #: 38-00763-A
24
PRELIMINARY
CY7C1355V25 CY7C1357V25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
25
PRELIMINARY
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
CY7C1355V25 CY7C1357V25
51-85115
Revision History
Document Title: CY7C1355V25/CY7C1357V25 Document Number:38-00763 REV. ** *A ECN NO. 2563 2682 ISSUE DATE 4/29/99 9/10/99 ORIG. OF CHANGE SKX SKX DESCRIPTION OF CHANGE 1. New Data Sheet 1. Updated the BGA pinout 2. Added revision history
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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